1. Field of the Invention
The present invention is directed to a monolithic integrated circuit comprising circuit branches which are parallel to one another and which lie between first and second circuit points, each of the branches containing one or more field effect transistors.
2. Description of the Prior Art
In circuit regions of the type generally set forth above with which, for example, gate functions of logic circuit technology are realized, there is the difficulty that an interruption error (open error) in one of the parallel circuit branches is difficult to identify by way of the standard methods for automatic error recognition. In particular, these methods are based on the fact that the inputs of the circuit to be checked are supplied with a sequence of test bit patterns, at least one of such bit patterns being of such a nature that it suitable for the recognition of a specific circuit error, i.e. leads to an output bit pattern at the circuit outputs which departs in terms of at least one bit from a reference bit pattern to be expected at the output when there are no errors.
If an open error is to be recognized in a defined parallel circuit branch, however, it is not adequate to supply a test bit pattern to the circuit input, this test bit pattern being individually assigned to this error. On the contrary, the circuit must be previously placed into a preparatory state by applying an initialization bit pattern, this preparatory state being likewise individually assigned to this error.
Since, when a test bit pattern deviating from the individually assigned test bit pattern is applied, the preparatory state can, in turn, be canceled, entire sequences each composed of an initialization bit pattern and of a test bit pattern appertaining thereto and following immediately thereupon must be applied to the circuit inputs in order to be able to investigate the parallel circuit branches individually for the presence of open errors.
The open errors in such circuits are essentially caused by the severing of interconnects at the edges of the field oxide layers, by deficient contactings between the terminal regions of the field effect transistors and the assigned connecting lines, and by the deposit of contaminating particles during circuit manufacture. These problems thereby appear to an increasing degree given progressive miniaturization of the circuit structures.